Embodiments of the present invention relate to a metal thin film connection structure, a manufacturing method thereof, and an array substrate.
A liquid crystal display is a flat panel display in common currently. Thin film transistor liquid crystal displays (TFT-LCDs) tend to dominate the current flat panel display market.
An array substrate is an important component of a liquid crystal display. FIG. 3a is a diagram showing the structure of an array substrate, and FIG. 3b is a partial enlarged view showing a metal thin film connection structure in FIG. 3a. As shown in FIGS. 3a and 3b, the array substrate comprises a pixel region 1 and a wiring region 2 which is located at the periphery of the pixel region 1. The array substrate comprises a base substrate 21 and a metal thin film connection structure formed thereon. A first metal layer pattern 22 is formed on the base substrate 21, an interlayer insulating layer is formed on the first metal layer pattern 22, a second metal layer pattern 24 is formed on the interlayer insulating layer, and an outer insulating layer is formed on the second metal layer pattern 24 (the interlayer insulating layer and the outer insulating layer are not shown in FIGS. 3a and 3b). The first metal layer pattern 22 may comprise a gate line, a common electrode line and a reparation line; and the second metal layer patter 24 may comprise a data line, a common electrode connecting line and a reparation line. The metal thin film connection structure 29 is located within the wiring region 2, and its enlarged view is shown in FIG. 3b. The metal thin film connection structure 29 comprises a plurality of columns of first via holes 26, and each column comprises a plurality of first via holes 26. The first via holes 26 are formed in the interlayer insulating layer and the outer insulating layer, and only the first metal layer pattern 22 is formed under the first via holes, and the second metal layer pattern is not. The metal thin film connection structure 29 comprises a plurality of columns of second via holes 27, and each column comprises a plurality of second via holes 27. The second via holes 27 are formed in the outer insulating layer and on the second metal layer pattern 24. A third metal layer pattern 28 is formed integrally on the outer insulating layer, and connects the first metal layer pattern 22 and the second metal layer 24 through the first via holes 26 and the second via holes 27.
During the process for designing and manufacturing an array substrate, a part of the first metal layer pattern 22 and a part of the second metal layer pattern 24 in the wiring region 2 are needed to be connected with each other. The above mentioned configuration incurs a problem that the third metal layer pattern 28 between the first via holes 26 and the second via holes 27 in the metal thin film connection structure 29 is likely overheated and burned out. FIG. 3c is an equivalent circuit diagram of the metal thin film connection structure in FIG. 3b. As shown in FIGS. 3b and 3c, because the resistances of first and second metal layer patterns 22 and 24 are much smaller than that of the third metal layer pattern 28, the resistances of the first and second metal layer patterns 22 and 24 can be omitted in FIG. 3c. In the equivalent circuit diagram in FIG. 3c, R1 and R2 are the equivalent resistors of the parts of the third metal layer pattern 28 over the second via holes 27, R5 and R6 are the equivalent resistors of the parts of the third metal layer pattern 28 over the first via holes 26, R3 and R4 are the equivalent resistors of the parts of the third metal pattern 28 between the first via holes 26 and the second via holes 27, R10 to R12 are the resistors having the contact resistances between the third metal layer pattern 28 and the first metal layer pattern 22 at the locations of the first via holes 26, and R7 to R9 are the resistors having the contact resistances between the third metal layer pattern 28 and the second metal layer pattern 24 at the locations of the second via holes 27. It can be seen from FIG. 3c that, among the currents flowing through the resistors, the current flowing through the R3 and R4 is concentrated, and the overheating and burning out tend to occur at the locations of the R3 and R4. Since the R3 and R4 are the equivalent resistors of the third metal layer pattern 28 between the first via holes 26 and the second via holes 27, the third metal layer pattern 28 between the first via holes 26 and the second via holes 27 is easily to be overheated and burned out.